1. Field of the Invention
This invention relates to frequency dividers that divide a set of multiphase signals such that the multiphase characteristic of having a monotonic and equally spaced phase increase with 50% duty cycle is still maintained in the divided multiphase output signals.
2. Description of Background
A multiphase signal is defined as a set of sinusoidal or rectangular signals with the individual signal components having equally spaced phase differences and a monotonic increase of phase when going from one signal to the next one. A typical example of a multiphase signal generator is a ring oscillator used for instance as voltage-controlled oscillator (VCO) in a phase-locked loop circuit (PLL). Such a ring oscillator consists of a ring of N identical delay cells each having a delay of τD. The oscillation frequency is then given by fosc=1/T=1/2NτD. If each delay cell output is fed to the output of the VCO, the oscillator provides N output signals each oscillating with fosc but also each having a phase difference of 2π/N with respect to its neighboring signal. The total of N signals is termed multiphase signal whereas the phase of the individual signals monotonically increases by the equal spacing of 2π/N when going from one signal to the next one. In terms of time units the phase differences between the individual components of the multiphase signal can also be expressed as T/N where T denotes the period of the multiphase signal.
A conventional multiphase divider is shown in FIG. 1. It consists of N toggle flip-flops according to the N components of the multiphase input signal. All of the toggle flip-flops are operated in parallel to each other. They are implemented as D-flip flops with a cross-connected feedback path from the inverting output Qb to the data input D. By cascading M of these toggle flip-flops a frequency division ratio of M can be obtained. The concatenation is carried out by connecting the non-inverting output Q of the previous divider stage to the clock input of the D-flip flop belonging to the succeeding divider stage. As will be explained in more detail below the straightforward implementation as shown in FIG. 1 has the drawback of suffering from a so-called phase ambiguity problem. That phase ambiguity problem is associated to the cross-connected feedback path (connection from Qb to D) in the toggle flip-flops that can assume an arbitrary state (either logical one or zero) at start-up and is a consequence of the mutual independency of the individual dividers. Because of this non-well defined initial state the dividers may start dividing in such a way that the divided output signal is no longer a valuable multiphase signal as the characteristic of having a monotonic increase of equally spaced phases got lost. This characteristic is however of great importance for the application of a multiphase division as will be explained below.
FIG. 2 shows another multiphase divider configuration known in the art. This multiphase divider consists of a set of resetable dividers and a reset delay circuit, which is clocked by one of the multiphase input signals and delays a reset signal coming from an external source. The dividers only take one out of N multiphase signals for the division. To generate a plurality of divided multiphase signals at their output, each of the individual dividers receive a reset signal from the reset delay circuit, which is basically a shift register (sequential logic) for the reset signal and thereby defines the starting point for the division of each individual divider such that the divided outputs are appropriately time-shifted to represent the desired divided multiphase phase signal. The shortcoming of this prior art configuration is that a true multiphase division is not performed but rather a single phase division because only one out of N multiphase inputs is actually used for the division. Consequently, the phase ambiguity problem does not occur; however, the division scheme completely relies on a single phase of the multiphase input. If the phase signal is affected by timing jitter or duty cycle distortion, all of the divided multiphase outputs are affected in the same way, which may be detrimental to the application of such a multiphase divider in a serial link receiver. Moreover, the duty cycle distortion may become a problem because one of the multiphase signals at the input will be much more loaded (higher driving capacity) than all the others because that single phase signal has to drive all of the dividers and also provides the clock for the reset delay circuit. Furthermore, the timing of the multiphase output may also be affected to a certain degree by the timing accuracy of the shift register in the reset delay circuit.
The implementation of a multiphase divider is not as straightforward as it is compared to the case when just having to divide a single-ended or a differential signal. A phase ambiguity problem occurs because of the mutual independency of the dividers when only using a number of conventional dividers in parallel.
When a multiphase signal consisting of, for example, six phases is divided by means of three parallel differential conventional dividers, the divided outputs may have phase ambiguity. An exemplary graph of such phase ambiguity is shown in FIG. 3. It can be seen that the important requirement of having the phases of the six signals monotonically increasing is violated because two out of the six signals got swapped during the division. The incorrect phases are encircled with a dashed circle. The dashed straight line indicates how the individual phases should run if they were a correct multiphase signal with monotonic phase increase and equal spacing between the individual phases. The swapping can be regarded as a 180-degree phase shift applied to the corresponding signals. This is an example of the phase ambiguity problem that is caused by the fact that the feedback paths in a conventional divider (typically implemented as a cross-coupled feedback connected D-flip flop also known as toggle flip flop) either assumes a 0-degree (e.g. logical 0) or a 180-degree (e.g. logical 1) state with respect to the pertinent input signal.
One solution to the phase ambiguity problem is to have the parallel dividers be dependent on each other. However, this approach suffers from requiring the introduction of internal feedback loops that may affect the required 50% duty cycle requirement, which is of great importance to prevent bimodal jitter effects in a half-rate receiver architecture. Another solution is to have appropriate startup conditions that remedy these shortcomings.
Currently, no designs employ a multiphase divider in their feedback path from the VCO to the phase detector in order to make the phase-rotating PLL (P-PLL) a frequency multiplying PLL. Since no feedback divider is used (the feedback division ratio equals 1 in that case), most current designs have to use a reference signal for the P-PLL that equals in frequency the output signals of the P-PLL used to drive the sampling latches in the serial link receiver.
If for instance the serial data stream is transmitted at 10 Gb/s, the P-PLL needs to provide a 5 GHz multiphase signal with a perfect 50% duty cycle if the serial link receiver is of a half-rate architecture with 3-fold oversampling per bit and a multiphase signal consisting of 6 phases is assumed. As a consequence thereof, the reference signal of the P-PLL also needs to be at 5 GHz for this 10 Gb/s serial link. Typically there are tens or hundreds of serial links on a chip that all need to receive a reference signal for their P-PLL type of link receiver. Distributing for instance a 5 GHz clock signal to all of these many link receivers consumes a considerable amount of power because the power consumption P is in a first order proportional to the frequency (P=C·VDD2·f where C denotes the load capacitance, VDD the supply voltage and f the frequency). Reducing the frequency of the reference clock signal would therefore help save a lot of power.